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| ON Semiconductort Octal Bus Buffer Inverting The MC74VHC540 is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC540 features inputs and outputs on opposite sides of the package and two AND- active- low output enables. When either -ed OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. * High Speed: tPD = 3.7ns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 4A (Max) at TA = 25C * High Noise Immunity: VNIH = VNIL = 28% VCC * Power Down Protection Provided on Inputs * Balanced Propagation Delays * Designed for 2V to 5.5V Operating Range * Low Noise: VOLP = 1.2V (Max) * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 2000V; Machine Model > 200V * Chip Complexity: 124 FETs or 31 Equivalent Gates MC74VHC540 DW SUFFIX 20--LEAD SOIC WIDE PACKAGE CASE 751D--05 DT SUFFIX 20--LEAD TSSOP PACKAGE CASE 948E--02 M SUFFIX 20--LEAD SOIC EIAJ PACKAGE CASE 967--01 ORDERING INFORMATION SOIC WIDE MC74VHCXXXDW TSSOP MC74VHCXXXDT SOIC EIAJ MC74VHCXXXM PIN ASSIGNMENT OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 * These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative. FUNCTION TABLE Inputs OE1 L L H X OE2 L L X H A L H X X Output Y H L Z Z (c) Semiconductor Components Industries, LLC, 2006 March, 2006 - Rev. 3 - 1 Publication Order Number: MC74VHC540/D LOGIC DIAGRAM A1 A2 A3 DATA INPUTS A4 A5 A6 A7 A8 OUTPUT ENABLES OE1 OE2 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 INVERTING OUTPUTS http://onsemi.com 2 MAXIMUM RATINGS* Symbol VCC Vin Vout IIK IOK Iout ICC PD Tstg DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package Parameter Value - 0.5 to + 7.0 - 0.5 to + 7.0 - 0.5 to VCC + 0.5 -- 20 20 25 75 500 450 - 65 to + 150 Unit V V V mA mA mA mA mW _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high--impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin Vout TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 3.3V 0.3V VCC =5.0V 0.5V Parameter Min 2.0 0 0 -- 40 0 0 Max 5.5 5.5 VCC + 85 100 20 Unit V V V _C ns/V DC ELECTRICAL CHARACTERISTICS Symbol VIH Parameter Minimum High--Level Input Voltage Maximum Low--Level Input Voltage Minimum High--Level Output Voltage Vin = VIH or VIL IOH = -- 50A Vin = VIH or VIL IOH = -- 4mA IOH = -- 8mA VOL Maximum Low--Level Output Voltage Vin = VIH or VIL IOL = 50A Vin = VIH or VIL IOL = 4mA IOL = 8mA Test Conditions VCC V 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 TA = 25C Min 1.50 VCC x 0.7 0.50 VCC x 0.3 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V Typ Max TA = - 40 to 85C Min 1.50 VCC x 0.7 0.50 VCC x 0.3 Max Unit V VIL V VOH V http://onsemi.com 3 DC ELECTRICAL CHARACTERISTICS Symbol Iin IOZ Parameter Maximum Input Leakage Current Maximum Three--State Leakage Current Maximum Quiescent Supply Current Test Conditions Vin = 5.5V or GND Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND VCC V 0 to 5.5 5.5 TA = 25C Min Typ Max 0.1 0.25 TA = - 40 to 85C Min Max 1.0 2.5 Unit A A ICC 5.5 4.0 40.0 A AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25C Symbol tPLH, tPHL Parameter Maximum Propagation Delay, A to Y (Figures 1 and 3) Test Conditions VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 3.3 0.3V (Note 1) VCC = 5.0 0.5V (Note 1) Cin Cout Maximum Input Capacitance Maximum Three--State Output Capacitance (Output in High Impedance State) CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 4 6 Min Typ 4.8 7.3 3.7 5.2 6.8 9.3 4.7 6.2 11.2 6.0 Max 7.0 10.5 5.0 7.0 10.5 14.0 7.2 9.2 15.4 8.8 1.5 1.0 10 10 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.5 12.0 6.0 8.0 12.5 16.0 8.5 10.5 17.5 10.0 ns ns pF pF ns ns Unit ns tPZL, tPZH Output Enable TIme, OEn to Y (Figures 2 and 4) tPLZ, tPHZ Output Disable Time, OEn to Y (Figures 2 and 4) tOSLH, tOSHL Output to Output Skew Typical @ 25C, VCC = 5.0V 17 CPD Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm -- tPLHn|, tOSHL = |tPHLm -- tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/8 (per bit). CPD is used to determine the no--load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 0.9 -- 0.9 Max 1.2 -- 1.2 3.5 1.5 Unit V V V V http://onsemi.com 4 SWITCHING WAVEFORMS VCC VCC A tPHL 50% VCC Y 50% tPLH GND Y 50% VCC VOL +0.3V Y tPZH 50% VCC tPHZ VOH --0.3V HIGH IMPEDANCE OE1 or OE2 50% tPZL tPLZ 50% GND HIGH IMPEDANCE Figure 1. Figure 2. TEST CIRCUITS TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST OUTPUT TEST POINT 1k CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Figure 4. INPUT EQUIVALENT CIRCUIT INPUT http://onsemi.com 5 OUTLINE DIMENSIONS DW SUFFIX SOIC CASE 751D-05 ISSUE F D A 11 X 45 _ NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ H M B M 20 10X 0.25 E 1 10 h 20X B 0.25 M B TA S B S A e SEATING PLANE 18X A1 T C DIM A A1 B C D E e H h L http://onsemi.com 6 L OUTLINE DIMENSIONS DT SUFFIX TSSOP CASE 948E-02 ISSUE A 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 20 11 K K1 B J J1 SECTION N-N L PIN 1 IDENT 1 10 --U- N 0.15 (0.006) T U S 0.25 (0.010) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ A --VN F DETAIL E C D 0.100 (0.004) - - SEATING -TPLANE --WG H DETAIL E http://onsemi.com 7 OUTLINE DIMENSIONS M SUFFIX SOIC EIAJ CASE 967-01 ISSUE O 20 11 LE Q1 M_ L DETAIL P E HE 1 10 Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.81 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.032 c b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800--282--9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082--1312 USA Phone: 480--829--7710 or 800--344--3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2--9--1 Kamimeguro, Meguro--ku, Tokyo, Japan 153--0051 Fax: 480--829--7709 or 800--344--3867 Toll Free USA/Canada Phone: 81--3--5773--3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC74VHC540/D |
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